W78LE58/W78L058A
8-BIT MICROCONTROLLER
Table of Contents-
1.
2.
3.
4.
5.
6.
7.
8.
9.
GENERAL DESCRIPTION .............................................................................................................. 2
FEATURES...................................................................................................................................... 2
PIN CONFIGURATIONS ................................................................................................................. 3
PIN DESCRIPTION ......................................................................................................................... 4
FUNCTIONAL DESCRIPTION ........................................................................................................ 5
SECURITY..................................................................................................................................... 17
ABSOLUTE MAXIMUM RATINGs................................................................................................. 18
DC CHARACtERISTICS................................................................................................................ 19
AC CHARACTERISTICS............................................................................................................... 21
10. TIMING WAVEFORMS.................................................................................................................. 23
11. TYPICAL APPLICATION CIRCUIT ............................................................................................... 25
11.1
Expanded External Data Memory and Oscillator ............................................................ 26
12. PACKAGE DIMENSIONS.............................................................................................................. 27
13. REVISION HISTORY..................................................................................................................... 34
-1-
Publication Release Date: December 4, 2006
Revision A6
W78LE58/W78L058A
1. GENERAL DESCRIPTION
The W78L058A is an 8-bit microcontroller which has an in-system programmable Flash EPROM for
firmware updating. The instruction set of the W78L058A is fully compatible with the standard 8052.
The W78L058A contains a 32K bytes of main ROM and a 4K bytes of auxiliary ROM which allows the
contents of the 32KB main ROM to be updated by the loader program located at the 4KB auxiliary
ROM; 512 bytes of on-chip RAM; four 8-bit bi-directional and bit-addressable I/O ports; an additional
4-bit port P4; three 16-bit timer/counters; a serial port. These peripherals are supported by a eight
sources two-level interrupt capability. To facilitate programming and verification, the ROM inside the
W78L058A allows the program memory to be programmed and read electronically. Once the code is
confirmed, the user can protect the code for security.
The W78L058A microcontroller has two power reduction modes, idle mode and power-down mode,
both of which are software selectable. The idle mode turns off the processor clock but allows for
continued peripheral operation. The power-down mode stops the crystal oscillator for minimum power
consumption. The external clock can be stopped at any time and in any state without affecting the
processor.
2. FEATURES
•
Fully static design 8-bit CMOS microcontroller
•
32K bytes of in-system programmable Flash EPROM for Application Program (APROM)
•
4K bytes of auxiliary ROM for Loader Program (LDROM)
•
512 bytes of on-chip RAM. (including 256 bytes of AUX-RAM, software selectable)
•
64K bytes program memory address space and 64K bytes data memory address space
•
Four 8-bit bi-directional ports
•
One 4-bit multipurpose programmable port
•
Three 16-bit timer/counters
•
One full duplex serial port
•
Eight-sources, two-level interrupt capability
•
Built-in power management
•
Code protection
•
Packaged in
−
Lead Free (RoHS) DIP 40:
W78L058A24DL
−
Lead Free (RoHS) PLCC 44: W78L058A24PL
−
Lead Free (RoHS) PQFP 44: W78L058A24FL
-2-
W78LE58/W78L058A
3. PIN CONFIGURATIONS
40-Pin DIP
T2, P1.0
T2EX, P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
RST
RXD, P3.0
TXD, P3.1
INT0, P3.2
INT1, P3.3
T0, P3.4
T1, P3.5
WR, P3.6
RD, P3.7
XTAL2
XTAL1
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
VDD
P0.0, AD0
P0.1, AD1
P0.2, AD2
P0.3, AD3
P0.4, AD4
P0.5, AD5
P0.6, AD6
P0.7, AD7
EA
ALE
PSEN
P2.7, A15
P2.6, A14
P2.5, A13
P2.4, A12
P2.3, A11
P2.2, A10
P2.1, A9
P2.0, A8
44-Pin PLCC
/
I
N
T
3
,
P
4 V
. D
2 D
44-Pin QFP
T
2
E
X
,
P
1
.
1
/
I
N
T
3
,
P
4 V
. D
2 D
P
1
.
4
P
1
.
3
P
1
.
2
T
2
E
X
,
P
1
.
1
T
2
,
P
1
.
0
A
D
0
,
P
0
.
0
A
D
1
,
P
0
.
1
A
D
2
,
P
0
.
2
A
D
3
,
P
0
.
3
P1.5
P1.6
P1.7
RST
RXD, P3.0
INT2, P4.3
TXD, P3.1
INT0, P3.2
INT1, P3.3
T0, P3.4
T1, P3.5
1
2
P
1
.
4
P
1
.
3
P
1
.
2
T
2
,
P
1
.
0
A
D
0
,
P
0
.
0
A
D
1
,
P
0
.
1
A
D
2
,
P
0
.
2
A
D
3
,
P
0
.
3
P1.5
P1.6
P1.7
RST
RXD, P3.0
INT2, P4.3
TXD, P3.1
INT0, P3.2
INT1, P3.3
T0, P3.4
T1, P3.5
6 5 4 3 2 1 44 43 42 41 40
7
39
38
8
37
9
36
10
35
11
34
12
33
13
32
14
31
15
30
16
29
17
18 19 20 21 22 23 24 25 26 27 28
P
3
.
6
,
/
W
R
P
3
.
7
,
/
R
D
X
T
A
L
2
X
T
A
L
1
V
S
S
P
4
.
0
P
2
.
0
,
A
8
P
2
.
1
,
A
9
P
2
.
2
,
A
1
0
P
2
.
3
,
A
1
1
P
2
.
4
,
A
1
2
P0.4, AD4
P0.5, AD5
P0.6, AD6
P0.7, AD7
EA
P4.1
ALE
PSEN
P2.7, A15
P2.6, A14
P2.5, A13
44 43 42 41 40 39 38 37 36 35 34
33
32
31
3
30
4
29
5
28
6
27
7
26
8
9
25
10
24
23
11
12 13 14 15 16 17 18 19 20 21 22
P
3
.
6
,
/
W
R
P
3
.
7
,
/
R
D
X
T
A
L
2
X V
T S
A S
L
1
P
4
.
0
P
2
.
0
,
A
8
P
2
.
1
,
A
9
P
2
.
2
,
A
1
0
P
2
.
3
,
A
1
1
P
2
.
4
,
A
1
2
P0.4, AD4
P0.5, AD5
P0.6, AD6
P0.7, AD7
EA
P4.1
ALE
PSEN
P2.7, A15
P2.6, A14
P2.5, A13
-3-
Publication Release Date: December 4, 2006
Revision A6
W78LE58/W78L058A
4. PIN DESCRIPTION
SYMBOL
TYPE
I
DESCRIPTIONS
EXTERNAL ACCESS ENABLE: This pin forces the processor to execute the
external ROM. The ROM address and data will not be presented on the bus if
the
EA
pin is high.
PROGRAM STORE ENABLE:
PSEN
enables the external ROM data in the
Port 0 address/data bus. When internal ROM access is performed, no
PSEN
strobe signal outputs originate from this pin.
ADDRESS LATCH ENABLE: ALE is used to enable the address latch that
separates the address from the data on Port 0. ALE runs at 1/6th of the
oscillator frequency.
RESET: A high on this pin for two machine cycles while the oscillator is
running resets the device.
CRYSTAL 1: This is the crystal oscillator input. This pin may be driven by an
external clock.
CRYSTAL 2: This is the crystal oscillator output. It is the inversion of XTAL1.
GROUND: ground potential.
POWER SUPPLY: Supply voltage for operation.
EA
PSEN
O H
ALE
O H
RST
XTAL1
XTAL2
V
SS
V
DD
P0.0−P0.7
P1.0−P1.7
P2.0−P2.7
P3.0−P3.7
P4.0−P4.3
I L
I
O
I
I
I/O D PORT 0: Function is the same as that of standard 8052.
I/O H PORT 1: Function is the same as that of standard 8052.
I/O H
PORT 2: Port 2 is a bi-directional I/O port with internal pull-ups. This port also
provides the upper address bits for accesses to external memory.
I/O H PORT 3: Function is the same as that of the standard 8052.
I/O H PORT 4: A bi-directional I/O. See details below.
* Note: TYPE
I: input, O: output, I/O: bi-directional, H: pull-high, L: pull-low, D: open drain
-4-
W78LE58/W78L058A
5. FUNCTIONAL DESCRIPTION
The W78L058A architecture consists of a core controller surrounded by various registers, four general
purpose I/O ports, one special purpose programmable 4-bits I/O port, 512 bytes of RAM, three
timer/counters, a serial port. The processor supports 111 different opcodes and references both a 64K
program address space and a 64K data storage space.
RAM
The internal data RAM in the W78L058A is 512 bytes. It is divided into two banks: 256 bytes of
scratchpad RAM and 256 bytes of AUX-RAM. These RAMs are addressed by different ways.
•
RAM 0H−7FH can be addressed directly and indirectly as the same as in 8051. Address pointers
are R0 and R1 of the selected register bank.
•
RAM 80H−FFH can only be addressed indirectly as the same as in 8051. Address pointers are R0,
R1 of the selected registers bank.
•
AUX-RAM 0H−FFH is addressed indirectly as the same way to access external data memory with
the MOVX instruction. Address pointer are R0 and R1 of the selected register bank and DPTR
register. An access to external data memory locations higher than FFH will be performed with the
MOVX instruction in the same way as in the 8051. The AUX-RAM is disable after a reset. Setting
the bit 4 in CHPCON register will enable the access to AUX-RAM. When AUX-RAM is enabled the
instructions of "MOVX @Ri" will always access to on-chip AUX-RAM. When executing from internal
program memory, an access to AUX-RAM will not affect the Ports P0, P2,
WR
and
RD
.
Example,
CHPENR
REG
F6H
CHPCON
REG
BFH
MOV
CHPENR,#87H
MOV
CHPENR,#59H
ORL
CHPCON,#00010000B ; enable AUX-RAM
MOV
CHPENR,#00H
MOV
R0,#12H
MOV
A,#34H
MOVX @R0,A
; Write 34h data to 12h address.
Timers 0, 1, and 2
Timers 0, 1, and 2 each consist of two 8-bit data registers. These are called TL0 and TH0 for Timer 0,
TL1 and TH1 for Timer 1, and TL2 and TH2 for Timer 2. The TCON and TMOD registers provide
control functions for timers 0, 1. The T2CON register provides control functions for Timer 2. RCAP2H
and RCAP2L are used as reload/capture registers for Timer 2. The operations of Timer 0 and Timer 1
are the same as in the W78C51. Timer 2 is a 16-bit timer/counter that is configured and controlled by
the T2CON register. Like Timers 0 and 1, Timer 2 can operate as either an external event counter or
as an internal timer, depending on the setting of bit C/T2 in T2CON. Timer 2 has three operating
modes: capture, auto-reload, and baud rate generator. The clock speed at capture or auto-reload
mode is the same as that of Timers 0 and 1.
-5-
Publication Release Date: December 4, 2006
Revision A6
